This invention relates to electronic component packaging and particularly to a ceramic carrier for housing and interconnecting a pair of semiconductor integrated circuit chips.
For most applications semiconductor integrated circuit chips are housed and interconnected in the now familiar dual-in-line package or close variants thereof. However, as the scale of integration has stepped up and the device density of the chips has increased there is greater need to improve and increase the compactness and efficiency of chip carriers. Carriers have been devised for mounting and connecting more than one chip as shown, for example, in U.S. Pat. No. 4,038,488. However, such tandem chip arrangements have not significantly reduced overall package dimensions or increased the degree of integration and density of packaged devices.